For relatively small integrated circuits, over-voltage I/O's and most radio frequency analog a typical electrostatic discharge (ESD) protection solution is the use of a local clamp. Typically a clamp is placed between the I/O pin or pad and ground. This acts as a short circuit path for high ESD pulse current in both directions. In the positive direction, the clamp provides high triggering voltage and is chosen according to the I/O signal range. In the negative direction, a diode (either an extra external diode, or an internal body diode such as the body diode of the triggering structure.
A typical triggering element for local CMOS ESD clamps is a so-called grounded gate snapback NMOS (GGNMOS), or its cascoded version that is used for overvoltage cell protection, as illustrated in FIG. 1, which shows a GGNMOS 10 protecting a driver circuit in the form of an invertor 12. In fact, in 80% to 90% of CMOS applications, grounded gate snapback N-MOS structures are the protection solution used. These work adequately during pulsed ESD operation but experience difficulties at continuous excessive currents or very high currents. The limited energy dissipation capabilities of grounded gate N-MOS ESD protection clamps can be attributed to the extremely localized region for heat dissipation, which corresponds to approximately a 0.5 μm region near the gate-drain region. Based on human body model (HBM) measurements, the peak critical power that can typically be handled by grounded gate N-MOS devices is no more than 50-100 mW per micron of contact width. Thus for a 6-8 V holding voltage, the current must not exceed 5-15 mA/μm. Nevertheless, because of their relatively small size, they continue to be commonly used in small integrated circuits, over-voltage I/O's and radio frequency analog applications.
In its simplest form, a N-MOS snapback device includes a gate defined by a poly layer, and a source and drain in the form of an n+ regions. A snapback GGNMOS device is characterized by an unsilicided drain ballasting region which defines a serial n+ distributed saturation resistance. A plot of the IV characteristics of such a snapback device is illustrated in FIG. 2. As mentioned above, the snapback device is characterized by the inclusion of a ballasting region. In the absence of a ballasting region, current would increase virtually unchecked after triggering at VTR 21 and only taper off at extreme currents due to increased resistance, as is shown by the curve 20. The IV characteristics of a distributed resistance such as the un-silicided portion is shown by curve 22 in FIG. 2, which shows a clear saturation current curve. The combined effect of including the ballast region for the snapback NMOS device is shown by curve 24. Thus the drain ballasting region 30, which typically has a length of approximately 3-6 μm and is shown in cross-section in FIG. 3, dumps the spatial current instability in the composite part of the GGNMOS. This built in saturation resistor region is already part of any snapback NMOS device and, after triggering due to an ESD pulse, GGNMOS has been shown to result in current saturation in the ballasting region 30.
However, while the ballasting region helps to limit spatial current fluctuations, its resistance causes an increased operation voltage of the ESD clamp as current increases. This increased voltage is presented to the internal circuitry 12 (FIG. 1) and can significantly exceed the critical voltage capabilities of the internal circuitry 12 under pulse conditions. According to Transmission Line Pulse (TLP) measurements, this is less of a concern for the GGNMOS device itself since the GGNMOS characteristics provide reliable ESD operation of more than twice the holding voltage value. However, this so-called VT2 value comes with a corresponding IT2 increase which results in critical dissipated power and a danger of thin oxide damage to the internal I/O driver 12 (which is presented as a CMOS invertor in FIG. 1). Typically this will occur much sooner than burnout of the GGNMOS.
Already in the case of 0.18 μm/3.3V technology but even more so with future scaling down which will result in reduced operating voltage and corresponding reduced gate oxide thickness and reduced breakdown voltage, the problem of how to build proper ESD snapback devices with the appropriate triggering characteristics and layout will become a challenge. This is especially true when high frequency issues are taken into account.